`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/10/18 23:28:44
// Design Name: 
// Module Name: time_div
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module time_div(
    input cp,
    input rst,
    output reg [1:0] out
    );
    reg [20:0] m;
    initial begin
        m=20'b0;
        out = 2'b0;
    end
    always @(posedge cp or negedge rst) begin
        if (rst==0) m =0;
        else if (m==30001) m=0;
        else m = m+1;
    end

	always@(posedge cp)
	begin
	    if(m==30000) //可通过更改条件值改变脉冲周期
            out= out + 1;
        else
            out=out;
    end
endmodule
